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features ? floating channel designed for bootstrap operation ? fully operational to +600v ? tolerant to negative transient voltage dv/dt immune ? gate drive supply range from 10 to 20v ? undervoltage lockout for both channels ? 3.3v logic compatible separate logic supply range from 3.3v to 20v logic and power ground 5v offset ? cmos schmitt-triggered inputs with pull-down ? cycle by cycle edge-triggered shutdown logic ? matched propagation delay for both channels ? outputs in phase with inputs high and low side driver product summary v offset 600v max. i o +/- 200 ma / 420 ma v out 10 - 20v t on/off (typ.) 125 & 105 ns delay matching 30 ns www.irf.com 1 data sheet no. pd60026 revs ir2112 ( - 1 - 2 )( s ) pbf description the ir2112(s) is a high voltage, high speed power mosfet and igbt driver with independent high and low side referenced output channels. proprietary hvic and latch immune cmos technologies enable rugge- dized monolithic construction. logic inputs are com- patible with standard cmos or lsttl outputs, down to 3.3v logic. the output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. propagation delays are matched to simplify use in high frequency applications. the floating channel can be used to drive an n-channel power mosfet or igbt in the high side configuration which operates up to 600 volts. (refer to lead assignments for correct pin configuration). this/these diagram(s) show electrical connections only. please refer to our application notes and designtips for proper circuit board layout. typical connection packages 14-lead pdip 16-lead soic (wide body)
ir2112 ( - 1 - 2 )( s ) pbf 2 www.irf.com note 1: logic operational for v s of -5 to +600v. logic state held for v s of -5v to -v bs . (please refer to the design tip dt97-3 for more details). note 2: when v dd < 5v, the minimum v ss offset is limited to -v dd . symbol definition min. max. units v b high side floating supply absolute voltage v s + 10 v s + 20 v s high side floating supply offset voltage note 1 600 v ho high side floating output voltage v s v b v cc low side fixed supply voltage 10 20 v lo low side output voltage 0 v cc v dd logic supply voltage v ss + 3 v ss + 20 v ss logic supply offset voltage -5 (note 2) 5 v in logic input voltage (hin, lin & sd) v ss v dd t a ambient temperature -40 125 c recommended operating conditions the input/output logic timing diagram is shown in figure 1. for proper operation the device should be used within the recommended conditions. the v s and v ss offset ratings are tested with all supplies biased at 15v differential. typical ratings at other bias conditions are shown in figures 36 and 37. v symbol definition min. max. units v b high side floating supply voltage -0.3 625 v s high side floating supply offset voltage v b - 25 v b + 0.3 v ho high side floating output voltage v s - 0.3 v b + 0.3 v cc low side fixed supply voltage -0.3 25 v lo low side output voltage -0.3 v cc + 0.3 v dd logic supply voltage -0.3 v ss + 25 v ss logic supply offset voltage v cc - 25 v cc + 0.3 v in logic input voltage (hin, lin & sd) v ss - 0.3 v dd + 0.3 dv s /dt allowable offset supply voltage transient (figure 2) 50 v/ns p d package power dissipation @ t a +25c (14 lead dip) 1.6 (16 lead soic) 1.25 r thja thermal resistance, junction to ambient (14 lead dip) 75 (16 lead soic) 100 t j junction temperature 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) 300 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage param- eters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. additional information is shown in figures 28 through 35. c/w w v c
ir2112 ( - 1 - 2 )( s ) pbf www.irf.com 3 symbol definition figure min. typ. max. units test conditions t on turn-on propagation delay 7 125 180 v s = 0v t off turn-off propagation delay 8 105 160 v s = 600v t sd shutdown propagation delay 9 105 160 v s = 600v t r turn-on rise time 10 80 130 t f turn-off fall time 11 40 65 mt delay matching, hs & ls turn-on/off 30 ns dynamic electrical characteristics v bias (v cc , v bs , v dd ) = 15v, c l = 1000 pf, t a = 25 c and v ss = com unless otherwise specified. the dynamic electrical characteristics are measured using the test circuit shown in figure 3. symbol definition figure min. typ. max. units test conditions v ih logic 1 input voltage 12 9.5 v il logic 0 input voltage 13 6.0 v oh high level output voltage, v bias - v o 14 100 i o = 0a v ol low level output voltage, v o 15 100 i o = 0a i lk offset supply leakage current 16 50 v b = v s = 600v i qbs quiescent v bs supply current 17 25 60 v in = 0v or v dd i qcc quiescent v cc supply current 18 80 180 v in = 0v or v dd i qdd quiescent v dd supply current 19 2.0 5.0 v in = 0v or v dd i in+ logic 1 input bias current 20 20 40 v in = v dd i in- logic 0 input bias current 21 1.0 v in = 0v v bsuv+ v bs supply undervoltage positive going 22 7.4 8.5 9.6 threshold v bsuv- v bs supply undervoltage negative going 23 7.0 8.1 9.2 threshold v ccuv+ v cc supply undervoltage positive going 24 7.6 8.6 9.6 threshold v ccuv- v cc supply undervoltage negative going 25 7.2 8.2 9.2 threshold i o+ output high short circuit pulsed current 26 200 250 v o = 0v, v in = v dd pw 10 s i o- output low short circuit pulsed current 27 420 500 v o = 15v, v in = 0v pw 10 s static electrical characteristics v bias (v cc , v bs , v dd ) = 15v, t a = 25 c and v ss = com unless otherwise specified. the v in , v th and i in parameters are referenced to v ss and are applicable to all three logic input leads: hin, lin and sd. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. a v ma v mv
ir2112 ( - 1 - 2 )( s ) pbf 4 www.irf.com functional block diagram com ho v s v cc lo v b lead definitions symbol description v dd logic supply hin logic input for high side gate driver output (ho), in phase sd logic input for shutdown lin logic input for low side gate driver output (lo), in phase v ss logic ground v b high side floating supply ho high side gate drive output v s high side floating supply return v cc low side supply lo low side gate drive output com low side return
ir2112 ( - 1 - 2 )( s ) pbf www.irf.com 5 lead assignments part number 14 lead pdip ir2112 16 lead soic (wide body) ir2112s 14 lead pdip w/o lead 4 ir2112-1 14 lead pdip w/o leads 4 & 5 ir2112-2
ir2112 ( - 1 - 2 )( s ) pbf 6 www.irf.com figure 1. input/output timing diagram figure 2. floating supply voltage transient test circuit figure 3. switching time test circuit figure 4. switching time waveform definition figure 6. delay matching waveform definitions figure 5. shutdown waveform definitions <50 v/ns
ir2112 ( - 1 - 2 )( s ) pbf www.irf.com 7 0 50 100 150 200 250 10 12 14 16 18 2 0 turn-on delay time (ns ) max . ty p. v cc /v bs supply voltage (v) 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 turn-on delay time (ns ) temperature figure 7a. turn-on time vs. temperature max. typ. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 turn-off delay time (ns ) temperature (c) figure 8a. turn-off time vs. temperature max. typ. 0 50 100 150 200 250 10 12 14 16 18 2 0 turn-off delay time (ns ) v cc /v bs supply voltage (v) max. typ. 0 100 200 300 400 0 2 4 6 8 101214161820 vdd supply voltage (v) turn-off delay time (ns) max. typ. figure 7b. turn-on time vs. v cc /v bs supply voltage figure 7c. turn-on time vs. v dd supply voltage figure 8b. turn-off time vs. v cc /v bs supply voltage figure 8c. turn-off time vs. v dd supply voltage 0 100 200 300 400 0 2 4 6 8 101214161820 turn-on delay time (ns ) vdd supply voltage (v) max. typ.
ir2112 ( - 1 - 2 )( s ) pbf 8 www.irf.com 0 50 100 150 200 250 10 12 14 16 18 20 shutdown delay time (ns) max. ty p. v cc /v bs supply voltage (v) 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 shutdown delay time (ns) temperature (c) figure 9a. shutdown time vs. temperature max. typ. 0 100 200 300 400 02468101214161820 v d d s uppl y v ol tage (v ) s hutdow n d el ay ti m e (ns) max. typ. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 turn-on rise time (ns ) temperature (c) figure 10a. turn-on rise time vs. temperature max. typ. 0 50 100 150 200 250 10 12 14 16 18 20 turn-on rise time (ns) vbias supply voltage (v) figure 10b. turn-on rise time vs. voltage max. typ. 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 turn-on fall time (ns) temperature (c) figure 11a turn-on fall time vs. temperature max. typ. figure 9b. shutdown delay time vs. v cc /v bs supply voltage figure 9c. shutdown time vs. v dd supply voltage
ir2112 ( - 1 - 2 )( s ) pbf www.irf.com 9 0 25 50 75 100 125 10 12 14 16 18 20 vbi a s s uppl y v ol tage (v ) turn-o f f fal l ti m e (ns) figure 11b. turn-off fall time vs. voltage max. typ. figure 12a. logic i input threshold vs. temperature 0 3 6 9 12 15 -50 -25 0 25 50 75 100 125 logic "1" input threshold (v) temperature (c) min. 03691215 2.5 5 7.5 10 12.5 15 17.5 20 logi c " 1 " i nput treshol d vdd logi c s uppl y v ol ta g e (v ) figure 12b. logic i input threshold vs. voltage min. 0 3 6 9 12 15 -50 -25 0 25 50 75 100 125 logic "0" input threshold (v) tem perature (c) figure 13a. logic 0 input threshold vs. temperature max. 0369121 5 2.5 5 7.5 10 12.5 15 17.5 20 logic " 0 " input treshold (v) vdd logic supply voltage (v) figure 13b. logic 0 input threshold vs. voltage max. 0 0.2 0.4 0.6 0.8 1 -50 -25 0 25 50 75 100 125 hi gh level o utput v ol tage (v ) tem perature max. figure 14a. high level output vs. temperature
ir2112 ( - 1 - 2 )( s ) pbf 10 www.irf.com figure 14b. high level output vs. voltage 0 0.2 0.4 0.6 0.8 1 10 12 14 16 18 20 vbai s s uppl y v otage (v ) hi gh level o u tp u t v o l tage (v ) max. 0 0.2 0.4 0.6 0.8 1 -50 -25 0 25 50 75 100 12 5 low level output voltage (v) temperature (c) max. figure 15a. low level output vs. temperature 0 0.2 0.4 0.6 0.8 1 10 12 14 16 18 2 0 low level output voltage (v) max. vbias supply votage (v) figure 15b. low level output vs. voltage 0 100 200 300 400 500 -50-25 0 25 50 75100125 offset supply leakage current (ua) max. figure 16a. offset supply current vs. temperature temperature (c) 0 100 200 300 400 500 0 100 200 300 400 500 600 offset supply leakage current (ua) max. vb boost voltage (v) figure 16b. offset supply current vs. voltage 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 vbs supply current (ua) temperature (c) figure 17a. v bs supply current vs. temperature max. typ.
ir2112 ( - 1 - 2 )( s ) pbf www.irf.com 11 figure 20a. logic i input current vs. temperature figure 17b. v bs supply current vs. voltage 0 20 40 60 80 100 10 12 14 16 18 20 vbs supply current (ua) max. typ. vbs floating supply voltage (v) 0 50 100 150 200 250 300 -50 -25 0 25 50 75 100 125 vcc supply current (ua) tem perature (c) max. typ. figure 18a. v cc supply current vs. temperature figure 18b. v cc supply current vs. voltage 0 50 100 150 200 250 300 10 12 14 16 18 20 vcc supply current (ua) vcc fixed supply voltage (v) max. typ. 0 2 4 6 8 10 12 -50-25 0 25 50 75100125 vdd supply current (ua) temperature (c) max. typ. figure 19a. v dd supply current vs. temperature figure 19b. v dd supply current vs. v dd voltage 0 2 4 6 8 10 12 0 2 4 6 8 10121416182 0 vdd supply current (ua ) vdd logic supply voltage (v) max. typ. 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 logic "1 " input bias current (ua) temperature (c) max. typ.
ir2112 ( - 1 - 2 )( s ) pbf 12 www.irf.com figure 20b. logic 1 input current vs. v dd voltage 0 20 40 60 80 100 02468101214161820 vdd logi c s uppl y v ol tage (v ) lo g ic " 1" in p ut bias current ( ua ) max. typ. 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 logic "0" input bias current (ua) tem p erature ( c ) figure 21a. logic 0 input current vs. tempera- ture max. figure 22. v bs undervoltage (+) vs. temperature max. typ. min. 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 vbs undervoltage lockout -(v ) temperature (c) figure 23. v bs undervoltage (-) vs. temperature max. typ. min. 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 vcc undervoltage lockout +(v) temperature (c) max. typ. min. figure 24. v cc undervoltage (-) vs. temperature figure 21b. logic 0 input current vs. v dd voltage 0 1 2 3 4 5 0 2 4 6 8 10121416182 0 logic "0" input bias current (ua) vdd supply voltage (v) max. 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 vbs undervoltage lockout +(v) temperature (c)
ir2112 ( - 1 - 2 )( s ) pbf www.irf.com 13 6 7 8 9 10 11 -50-250255075100125 vcc undervoltage lockout - (v) temperature (c) figure 25. v cc undervoltage (-) vs. temperature max. typ. min. 0 100 200 300 400 500 -50-25 0 255075100125 output source current (ma) temperature (c) figure 26a. output source current vs. temperature typ. min. figure 26b. output source current vs. voltage 0 100 200 300 400 500 10 12 14 16 18 20 output source current (ma) vbias supply voltage (v) typ. min. 0 150 300 450 600 750 -50 -25 0 25 50 75 100 125 output sink current (ma) temperature (c) figure 27a. output sink current vs. temperature typ. min. 0 150 300 450 600 750 10 12 14 16 18 20 vbias supply voltage (v) output sink current (ma) figure 27b. output sink current vs. voltage typ. min.
ir2112 ( - 1 - 2 )( s ) pbf 14 www.irf.com figure 28. ir2112 t j vs. frequency (irfbc20) r gate = 33 ? ? ? ? ? , v cc = 15v figure 29. ir2112 t j vs. frequency (irfbc30) r gate = 22 ? ? ? ? ? , v cc = 15v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v figure 33. ir2112s t j vs. frequency (irfbc30) r gate = 22 ? ? ? ? ? , v cc = 15v figure 32. ir2112s t j vs. frequency (irfbc20) r gate = 33 ? ? ? ? ? , v cc = 15v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v figure 31. ir2112 t j vs. frequency (irfpe50) r gate = 10 ? ? ? ? ? , v cc = 15v figure 30. ir2112 t j vs. frequency (irfbc40) r gate = 15 ? ? ? ? ? , v cc = 15v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v
ir2112 ( - 1 - 2 )( s ) pbf www.irf.com 15 figure 34. ir2112s t j vs. frequency (irfbc40) r gate = 15 ? ? ? ? ? , v cc = 15v figure 35. ir2112s t j vs. frequency (irfpe50) r gate = 10 ? ? ? ? ? , v cc = 15v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v figure 36. maximum v s negative offset vs. v bs supply voltage figure 37. maximum v ss positive offset vs. v cc supply voltage -15.0 -12.0 -9.0 -6.0 -3.0 0.0 10 12 14 16 18 20 v bs floating supply voltage (v) v s offset supply voltage (v) typ. 0.0 4.0 8.0 12.0 16.0 20.0 10 12 14 16 18 20 v cc fixed supply voltage (v) v ss logic supply offset voltage (v) typ.
ir2112 ( - 1 - 2 )( s ) pbf 16 www.irf.com 01-6010 01-3002 03 (ms-001ac) 14-lead pdip case outline 14-lead pdip w/o lead 4 01-6010 01-3008 02 (ms-001ac)
ir2112 ( - 1 - 2 )( s ) pbf www.irf.com 17 16-lead soic (wide body) 01 6015 01-3014 03 (ms-013aa) 16 lead pdip w/o leads 4 & 5 01-6015 01-3010 02
ir2112 ( - 1 - 2 )( s ) pbf 18 www.irf.com leadfree part marking information order information lead free released non-lead free released part number date code irxxxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code p ? marking code ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 this product has been qualified per industrial level data and specifications subject to change without notice. 3/23/2005 14-lead pdip ir2112 order ir2112pbf 14-lead pdip ir2112-1 order ir2112-1pbf 14-lead pdip ir2112-2 order ir2112-2pbf 16-lead soic ir2112s order ir2112spbf part only available leadfree

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